1. Field of the Invention
The present invention generally relates to integrated circuits, and more particularly to an integrated circuit package having a die with a unique lead configuration that allows a minimal number of signal layers to be used in the package substrate, and thereby realize a low cost integrated circuit package.
2. Discussion of the Related Art
As is known, there is a wide variety of computing devices that are designed from an even wider variety of integrated circuit devices. In years past, the primary concern among circuit designers was to design a circuit that achieved the appropriate and desired functionality for that circuit. While speed has always been one factor and concern in circuit design, the concerns in the past have primarily focused upon using faster and faster components and avoiding race conditions or other conflicts that may arise between different devices or integrated circuit packages.
Currently, however, clock and bus speeds have been driven to higher and higher levels (i.e., faster and faster speeds). This has raised new issues in circuit design. For example, previously the physical size of an integrated circuit package did not create design problems, except for the fact that generally smaller packages are desired to facilitate layout on a printed circuit board of a given size, improve power consumption, etc. In many contemporary systems, however, signal frequencies and transition speeds of electronic signals push the envelope with regard to the physical size of an integrated circuit chip. More specifically, fabrication technology (although ever-improving and allowing increasingly smaller integrated circuit packages) generally defines the size limit for a given integrated circuit package of a given transistor count. Within this given package size having a fixed latency, it has been found that there is a limit on the signal transition speed or frequency which can be handled by that package, without paying specific regard to the lead layout of the package.
To more specifically illustrate this concern, consider an integrated circuit chip of a ball grid array package type. As it is known, ball grid array circuit packages have a planer bottom face that is either square or rectangular in dimension. This face is generally covered with small spherical leads that carry electric signals to and from the integrated circuit that is a part of the chip or the integrated circuit package. As is known, the planar bottom forms part of a substrate (typically multi-layered substrate) to which an integrated circuit die is affixed. The signals on the substrate leads are communicated to and from the circuit die by way of smaller leads on the die.
Conventionally, these die leads have been disposed about the perimeter of the die. As a result, signals input on one lead and output on another lead often traveled entirely across the die. Although the die is relatively small in physical size, this size has nevertheless become a factor with regard to the higher signal frequencies of contemporary circuits. Therefore, without regard to the specific configuration or layout of these leads, a signal that passes through the chip may travel a distance that is roughly equal to the dimension of the chip (e.g., more specifically the height and width of the chip). Accordingly, this increases the latency of the chip, and since system design must be made from the "worst case" perspective, this lower latency is a limitation upon the speed that signals within the system may be driven.
Accordingly, it is desired to provide an improved lead configuration or layout for integrated circuit packages that results in lower latency times.